Jobbet "System Verilog / UVM Verification Engineer" er udløbet.
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- be part of an international IT - and Datacom company

Silicom Denmark has a UVVM simultation environment and due to new collaboration with Intel, Silicom will also work with UVM based verification.  

In order to strengthen the verification processes and the simultation environment in Silicom Denmark, the company is looking for an experienced System Verilog / UVM Verification Engineer, experienced with FPGAs, who will be responsible for creating and building a UVM simultation environment. This position is newly created.

As a new System Verilog / UVM Verification Engineer you will be responsible for and the driving force in creating and building a UVM simultation environment. 

In this position you will have the opportunity to gain influence and put your mark on the UVM simultations environment in Silicom Denmark. You will be part of a dedicated highly skilled FPGA team, and work closely together with the Team Leader, FPGA Designers and the other FPGA Veri-fication Verification engineer, who works with UVVM. The position reports to the VP of Solutions Engineering.

Primary tasks and responsibilities:

  • Create and build UVM simultation environment, including:
    -    writing test plans and other relevant verification documents
    -    creating testbenches and test cases
    -    creating agents
    -    creating scoreboards
  • Maintain an existing UVM simultation environment
  • Create scripts to automate the test procedures
  • Create and build  a UVM block and chip - level verification environment for multiple FPGAs 

Furthermore, we expect you to participate along with the FPGA designers to debug issues, when they occur. 

You will be the expert in the framework and way of working with verification in a UVM environment,  and you will support your colleagues in this.

Your profile includes:

  • Expert in System Verilog ( SV ) including Assertions ( SVA ) and functional Coverage
  • Expert in UVM and experience with UVVM
  • Experience with VHDL
  • Some experience with and knowledge of FPGAs 
  • Solid experience with verification requirements and test plans
  • Knowledge of and experience with scripting languages as TCL / Python
  • Knowledge of and experience with simultation tools
  • Experience with regression testing / continuous integration - experience with Jenkins 
  • Good debugging skills

The ideal candidate has an engineering background ( candidate- or bachelor degree ) within electronics, combined with experience in creating simultation environment in the electronic industry, e.g. IT, datacom or telecom. Very good skills in English, written and spoken.

How to apply:
Please apply online via the "Ansøg" link, for further information, you are welcome to contact Selsøe & Partners ApS: Helle Selsøe +45 2273 3013.

Please write in your application that you've seen the job at Jobfinder.