Gå til hovedindhold

Are you ready to further develop the most advanced digital hearing aids on the market? Join an expanding R&D IC team in Copenhagen and use your skills to help define the future of chipset architecture and CMOS technology.

Leading major technology shifts with intelligent audio solutions
At the headquarters of GN ReSound, part of GN Hearing in Copenhagen, you will be joining R&D IC a dynamic team of 26 designers that strive to develop leading chipsets for hearing applications. Together, we innovate and develop a wide variety of ultra-low-power mixed circuits in nanometer CMOS technologies from transistor-level to GDS and silicon.

As Senior IC Designer in the analog team, you will be:

  • Defining new mixed chip architectures
  • Driving high-level technical choices like foundry technology selection and chip partitioning
  • Steering concept studies in early project phase
  • Writing high-level specifications and review designers’ block-level specifications
  • Hands-on design of complex subsystems and transistor-level design of critical blocks
  • Participating in design reviews and take part in the chip tape-out decisions
  • Contributing to the chip qualification strategy in lab and wafer test

A position where you define the future of our chipsets
You will work alongside analog and digital IC designers, system designers specialized in audio processing and radio systems, a 3D integration team and technology providers. As principal engineer, you will be at the center of the projects and have a say in the future chipset designs and the improvement of our design methodologies.

Solid experience with CMOS
We seek a “can do” team player willing to thrive, to push innovation on the market and to make the team designing the best chipset in our business.

You hold a master’s degree or PhD in electronics engineering with emphasis on IC design and have at least 10 years of experience with CMOS analog or mixed design.

Further:

  • You have been in charge of subsystems like PLL, RFFE or DC-DC converter
  • You are an efficient user of EDA tools (Cadence/Mentor/Synopsys), augmented by automation of design tasks with some scripting language (python, TCL, Skill)
  • You are often using high-level analog modeling (verilogA)
  • You are familiar with CMOS fabrication and devices, their spice modeling and corner definition
  • You are familiar with sampled signal theory and analysis (Matlab, Python)
  • You have excellent communication skills in English

Would you like to know more?
To apply, use the ‘Ansøg’ link no later than 20th December 2019. Applications are assessed on a continuous basis, which is why we encourage you to send your application as soon as possible.

If you want to know more about the position, you are welcome to contact Mark Brooks, Director of IC Team, on: +45 4081 6670.

Please write in your application that you've seen the job at Jobfinder.