FPGA/ASIC manager
Do you want to be part of the development of the new future 5G mobile network?
FPGA/ASIC manager for MTI Radiocomp ApS
Position Descriptions
Education Required
- A Master of Science in Engineering or similar with focus on FPGA/ASIC design, signal processing and preferable knowledge about telecommunication systems and technologies.
Work Experience, Specialized Skills and Knowledge Required
- Minimum 10 years’ experience
- Documented managerial skills within people and project management.
- The Manager of Digital Processing is expected to drive our designs, be proficient in VHDL or Verilog and in FPGA/ASIC design flows. In addition, you will use various scripting languages like MATLAB, Perl, TCL, Bash, Batch and others in daily activities
Who are we
Do you want to be part of the development of the new future 5G mobile network? Do you want to be part of an international R&D site? Then join MTI Radiocomp. We are world leading in IP cores for mobile networks. We are an important competence center in the MTI group, working closely with our sister sites in California and Taiwan and with some of the very largest players in the industry. Through the forward-looking solutions developed, we target to influence upcoming 5G standards.
MTI Radiocomp is a dynamic company with innovative culture, with tradition for teamwork and idea sharing.
The job
Our Manager of Digital Processing within Radiocomp will become the leader of an energetic, engaged and professional FPGA/ASIC IP core team. You will be a key contributor to definition of ASIC/FPGA architecture and implementation for future projects. You will have a good opportunity to put your mark on the solutions coming out of the team.
The job will give you an in-depth knowledge of the newest design methodologies used in mobile networks, including signal processing, network technologies and protocols. Your team will be working closely together with our software team and the systems engineering team to reach the most innovative and smart designs.
The Manager of Digital Processing (FPGA/ASIC) shall manage a local team of highly skilled engineers with different competence areas. The manager has the overall responsibility of planning and scheduling team activities as well as people management. This includes maintaining a positive and inspiring work environment in the group, facilitating open communication, employee feedback and reviews.
You will be reporting to the global Manager of Digital Processing located in US.
The team
The ASIC/FPGA team is a part of the HW group and it consists of a highly skilled team distributed in our three locations in Taiwan, California and Denmark. The team is highly motivated, strives to deliver smart solutions to complicated problems.
Main tasks for the team you will lead:
- Development of the next generation of FPGA’s for 5G
- Beginning-to- end FPGA design
- IP soft core development, maintenance and support for ASICs
- Integrate algorithms into VHDL modules
- Support the software team in developing the HW drivers.
- Give input and spare with the system engineering team
- Documentation
Technical areas for the team you will lead:
- Signal processing: e.g. FIR filters, Sample Rate Conversion, etc.
- Protocols: RoE, CPRI, OBSAI, JESD204B, Ethernet
- Coding: Scrambling, 8b10b, 64b66b and Reed-Solomon
- Main scripting languages: Tcl, Perl, Batch and Bash.
- Main tools: Xilinx Vivado and ModelSim
Personal skills:
You are capable of driving our designs and you are proficient in VHDL or Verilog and in FPGA/ASIC design flows. In addition, you have a good command of various scripting languages like MATLAB, Perl, TCL, Bash and Batch.
Personally you strive to make a difference in our products. You are a systematic and solution oriented person that manages to bring structure and proper documentation with your design. You feel motivated by being the best within your field and you get inspired when working with your team. You a have a proven track of people management which you can successfully combine with technical work. You are open to different cultures and changes in an international environment.
Language skills:
Written and spoken English at high level.
Master of Science in Engineering with at least 10 years of experience.
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